Design-Reuse

Synopsys VCS Verilog Simulator Incorporates Breakthrough Verification Capabilities

MOUNTAIN VIEW, Calif.--(BUSINESS WIRE)--Sept. 26, 2001-- Synopsys, Inc. (Nasdaq:SNPS), the technology leader for complex IC design, today announced VCS(TM) 6.0.1, the latest release of the industry's ...
Nasdaq

Synopsys VCS Used by Graphcore to Verify Next-Generation Colossus GC200 IPU

MOUNTAIN VIEW, Calif., July 20, 2020 /PRNewswire/ -- Synopsys, Inc. (Nasdaq: SNPS) today announced that Graphcore used the Synopsys VCS® simulation solution with Verdi® debug to verify its recently ...
Electronic Design

Verilog Simulator Adds Full-Featured Coverage Analysis And A C/C++ Interface

The latest VCS Verilog simulator from Synopsys contains built-in comprehensive coverage analysis. With it, design teams using VCS 6.0.1 can determine their verification quality before tapeout.
Nasdaq

Synopsys Collaborates with Google Cloud to Broadly Scale Cloud-based Functional Verification

MOUNTAIN VIEW, Calif., Sept. 9, 2019 /PRNewswire/ -- Synopsys, Inc. (Nasdaq: SNPS) today announced a collaboration with Google Cloud to provide a full end-to-end solution to perform functional ...
Design-Reuse

Acacia Communications Reduces Simulation Regression Turnaround Time by 2X Using Synopsys VCS Fine-Grained Parallelism Technology for High-Speed Optical Interconnect SoCs

MOUNTAIN VIEW, Calif. -- May 18, 2017 -- Synopsys, Inc. (NASDAQ: SNPS) today announced that Acacia Communications has successfully deployed Synopsys VCS Fine-Grained Parallelism (FGP) technology in ...
Electronic Design

Testbench Automation Tool Provides Tight Links To Verilog Simulation

Faster runtime performance, real-time access to built-in Verilog simulation coverage metrics, and a unified graphical environment for waveform analysis are all ...
Semiconductor Engineering

Address Simulation Turn-Around Time Bottlenecks with VCS Fine-Grained Parallelism

Non-stop growth in design size and complexity makes it more difficult than ever for verification teams to keep up with project demands and product goals. According to the Synopsys 2017 Global User ...
EDN

Synopsys Announces Formal Verification Tool

Magellan Combines Formal Verification Engines with VCS to Find Deep Corner-Case Bugs and Enable Design for Verification MOUNTAIN VIEW, Calif.–May 12, 2003–Synopsys, Inc., the world leader in ...
Semiconductor Engineering

Simulation: Balancing Speed And Debug

There’s an old saying about simulation: “It’s all about the need for speed.” Simulation is the core technology for functional verification of semiconductors, and the demand for higher runtime ...