Electronic Design

VHDL/Verilog Simulator Shows 300% Speed Improvement

The new Active-HDL 4.2 Standard Edition shows a 300% simulation speed improvement over the previous 4.1 version for both VHDL and Verilog designs. Additionally, for Verilog designs, Active-HDL 4.2 ...
EDN

Symphony EDA rolls out VHDL simulator

SAN FRANCISCO — Hardware description language (HDL) simulation provider Symphony EDA has introduced VHDL Simili 3.0, a VHDL simulation environment that the company claims reduces verification cycle ...
EDN

EDA entrepreneur spins $750 VHDL simulator

Santa Cruz, Calif. — A part-time passion for affordable HDL simulation led Cypress Semiconductor engineer Haneef Mohammed to launch Symphony EDA, which last week rolled out what it calls a ...
Ars Technica

Open Source VHDL (or similar) CPU Simulation Software

Hey all, my last semester of college we had to develop the microarchitecture for a RISC processor. My group was ultimately unsuccessful (our L2 cache had some serious issues), but I wouldn't mind ...
Design-Reuse

Powerful FPGA Design Creation and Simulation IDE Adds VHDL-2019 Support & OSVVM Enhancements

Aldec’s Active-HDL™ enables FPGA designers to take full advantage of the many features within the latest revision to VHDL and helps improve design verification efficiency. Henderson, NV – January 20, ...
Design-Reuse

Synopsys speeds Verilog, VHDL simulation

MOUNTAIN VIEW, Calif. — Claiming substantial speedups in its Verilog and VHDL simulation products, Synopsys Inc. this week is announcing releases of its VCS Verilog and Scirocco VHDL simulators. The ...
Ars Technica

VHDL / HDL compiler and simulator

A question for any CpE/EE/CS students/grads out there: I am currently using Altera Max-Plus II, but on my windows box only because that is all it supports. However I was wondering if there are any ...
TechRepublic

Design and simulation of 16 Bit UART Serial Communication Module Based on VHDL

In this paper the authors describe the design of UART (Universal Asynchronous Receiver Transmitter) based on VHDL. As UART is consider as a low speed, low cost data exchange between computer and ...
Semiconductor Engineering

Racal Redac – VHDL simulator

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