Yahoo Finance

Achronix Introduces the Highest FPGA Memory Bandwidth, PCIe Acceleration Board for Data Center Applications

SANTA CLARA, CA--(Marketwired - June 21, 2016) - Achronix Semiconductor Corporation today announced the availability of the new PCIe form factor Accelerator-6D accelerator board which is the ...
Design-Reuse

Altera Starts Production Shipments of Industry's Highest Memory Bandwidth FPGA

The Agilex™ 7 FPGA M-Series Optimized to Reduce Memory Bottlenecks in AI and Data-intensive Applications. SAN JOSE, California, Apr. 4, 2025 – Altera Corporation, a leader in FPGA innovations, today ...
Design-Reuse

Minding network queues with FPGAs and memory

One of the major requirements in communication systems is quality-of-service (QoS). It is required in order to implement competitive service differentiation and is typically achieved through traffic ...
Electronic Design

M.2 Module Merges FPGA and 32-GB Memory

The PCI Express (PCIe) interface supports NVMe, which is de facto high-speed storage interface. The module supports computational storage processor (CSP) configurations—CSPs are becoming more popular ...
New Electronics

AMD validates Infineon’s HYPERRAM memory for FPGA evaluation kit

Infineon Technologies has confirmed that AMD successfully tested its 64 Mb HYPERRAM memory and HYPERRAM controller IP with the AMD Spartan UltraScale+ FPGA SCU35 Evaluation Kit. HYPERRAM memory ...
NextBigFuture

Ex-800 Blade server uses hybrid memory cubes for super data performance with lower power usage

A single HMC (Hybrid Memory Cube) can produce an incredible data bandwidth of 160 GBytes/sec, thereby providing more than 15 times the performance of a state-of-the-art DDR3 memory module while ...
EDN

Implementing custom DDR and DDR2 SDRAM external memory interfaces in FPGAs (part 2)

Note: This is the second part of a two-part article covers the remaining steps to implement DDR or DDR2 external memory interfaces (EMIFs) using FPGAs via ALTDLL and ALTDQ_DQS megafunctions. Steps 4 ” ...
EDN

Spartan-7 FPGA Configuration with SPI Flash and Bank 14 at 1.35V

This application note describes a method for configuring a Spartan®-7 FPGA from a 1.8V serial peripheral interface (SPI) NOR flash memory connected to the FPGA dedicated I/O bank 0 at 1.8V and ...