EDN

Cache and Memory Hierarchy Design

Developed a flexible cache simulator which implemented L1 cache, its Victim cache and L2 cache. Analyzed the performance of various memory hierarchy configurations with varying parameters and ...
Semiconductor Engineering

Redesigning Core and Cache Hierarchy For A General-Purpose Monolithic 3D System

A technical paper titled “RevaMp3D: Architecting the Processor Core and Cache Hierarchy for Systems with Monolithically-Integrated Logic and Memory” was published by researchers at ETH Zürich, KMUTNB, ...
EDN

SoC design: When a network-on-chip meets cache coherency

Many people have heard the term cache coherency without fully understanding the considerations in the context of system-on-chip (SoC) devices, especially those using a network-on-chip (NoC). To ...

Tensormesh and AMD Collaborate to Empower Fewer GPUs to Serve More Models

Tensormesh, the company pioneering caching-accelerated inference optimization for enterprise AI, today announced a ...
Semiconductor Engineering

Four-Tier Memory Hierarchy for LLM Reasoning (USC, UW)

A new technical paper, “Not All Thoughts Need HBM: Semantics-Aware Memory Hierarchy for LLM Reasoning,” was published by researchers at USC and University of Wisconsin-Madison. “Reasoning LLMs produce ...
The Next Platform

cache hierarchy

The gap between the performance of processors, broadly defined, and the performance of DRAM main memory, also broadly defined, has been an issue for at least three decades when the gap really started ...